Insys is about People involved in Research, Courses with Course material, PhD's and thesis

Insys Research

Desics
creating a world of smart networked devices

In the coming decade, our living environment will undergo a dramatic change. The dumb appliances of today will be upgraded with processing and communication power, connecting you to the world wherever you are. As a consequence, we will be surrounded and even carry networks of smart devices. IMEC is developing the key technologies for making this a reality: high performant, yet small, low-cost and low-power radios-in-a-package, design technologies for networks of mixed re-configurable hardware and programmable software devices, Quality-of-Service provisions for interactive multimedia applications. This development of key technologies is strongly supported by over 40 Ph.D. students and this number is growing continuously as the complexity of designing Systems-on-Chip increases exponentially over time. (more)

MCP
Microsystems, Components and Packaging Division

The Microsystems, Components and Packaging Division (MCP) at IMEC, is involved in research that ranges from fundamental materials and device processing, to that of the integration and packaging of functional sub-systems, modules and systems. The activities are driven by the long term vision of fulfilling the potential needs and requirements of tomorrow's world of ambient intelligence, 2D imaging devices, renewable energy systems and power electronics.
Functional prototype demonstrators for different system application are developed with an eye towards potential ease of manufacturing and their ability to lead to small business initiatives and entrepreneurial start-ups. (more)

SPDT
Silicon Process and Design Technology

In the IMEC Silicon divisions research and development is carried out on the materials, technological steps and modules, advanced structures and new components that will be needed for the next generations of deep-submicron CMOS integrated circuits. These activities are largely driven by the requirements as dictated by the acceleration of the ITRS roadmap (International technology Roadmap for Semiconductors) which predicts that for the future technology generations (90nm down to 32nm in 2013), the transistor gate length will continue to be scaled by a factor of 0.7 every 2 to 3 years. Recent predictions refer to MPU's by the year 2016 with transistor gate length of only 9nm and clock frequencies of 29GHz. (more)